1. Field of the Invention
The present invention relates to a method of manufacturing an insulating gate field-effect transistor. In particular, the present invention relates to a method of manufacturing a semiconductor device that can be applied to a thin film transistor (TFT) having a gate overlapping structure.
2. Related Art
A display device using a liquid crystal has been put to practical use in a 20-inch or more large-screen that is typified by liquid crystal display TV. In recent years, a liquid crystal display device integrated with driving circuit that comprises TFT in which a polycrystalline silicon film is used as an active layer is realized.
However, there is a problem that the TFT using a polycrystalline silicon film result in lower withstanding pressure of drain junction. It resulted that junction leak current (hereinafter, OFF-leak current) is increased. It is known that a lightly doped region (LDD) is effective for reducing the OFF-leak current.
The problem is pointed out that high electric field is generated at the vicinity of the drain region, then, hot carriers are trapped by a gate insulating film on the LDD region, and then, a device characteristic such as threshold value is greatly deteriorated. The TFT in which the gate electrode is overlapped with the LDD region to prevent the deterioration of hot carriers is disclosed in JP 2001-294787. The gate overlapped LDD structure TFT has higher current driving ability compared to the normal LDD structure TFT, and suppresses the deterioration due to hot carriers by easing effectively the high electric field at the vicinity of the drain region.
However, according to the gate overlapped LDD structure TFT disclosed in above publication, an impurity region for forming an LDD region is formed on the semiconductor layer, then, the gate electrode is formed thereon to overlap with the LDD region. The manufacturing method cannot regulate accurately the portion that is overlapping with the gate electrode along with the miniaturization of design rule.
On the other hand, the preferred example of manufacturing the gate overlapping LDD structure TFT in a self-aligning manner is disclosed in JP2002-14337. The technique disclosed in the publication is that at least two layered conductive layer is subjected to once exposure and plural etching, then, the upper layer and the lower layer are formed to have different thickness and shape, and then, an ion doping is conducted thereon. Consequently, an LDD region that is overlapped with a gate electrode can be formed in a self-aligning manner.
Of course, it is necessary that the LDD length (the length for channel length) is optimized depending on the driving voltage of TFT in order to maximize the functions of the LDD overlapped with the gate electrode as a countermeasure against deteriorations due to hot carriers. That is, there is optimum length for easing effectively the high electric field region in the vicinity of the drain region.
The technique disclosed in above-mentioned publication has two steps: in the first step, two laminated conductive layers are subjected to etching to have a taper shape, in the second step, only the upper layer of the laminated conductive layers in the taper shape is selectively subjected to anisotropic etching, and can regulate LDD length by controlling the taper angle.